In the well known type of phase locked loop which employs a dual flip-flop phase detector, the two flip-flops are respectively clocked by a reference frequency signal and a signal form a local oscillator which tracks the reference frequency. A feedback gate is connected to nominally simultaneously change the flip-flops back to their previous state after they have both been clocked during a given cycle of operation. For example, if the flip-flops are connected to assume the set state when they are clocked, the feedback gate resets them both as soon as both are set. Thus, if one of the input signals leads the other in phase, the flip-flop it clocks sets earlier than the other flip-flop, but they both are subsequently reset at the same time. (Ideally, the second flip-flop is reset instantaneously after it is set.) Therefore, an output pulse representing the period that the first-to-set flip-flop remains set can be interpreted by downstream circuitry, which includes a differential amplifier, to develop a correction signal to pull the local oscillator in the appropriate direction to seek phase lock. The dual flip-flop phase detector type of phase locked loop is very reliable in operation for applications in which circuit delay through the flip-flops and feedback gate can be ignored for the contemplated frequency range of operation.
However, for critical applications at higher frequencies, a subtle error, always present, becomes meaningful. The manifestation of this error is that, when the phase locked loop is in apparent phase lock, it is, instead operating with the two frequency signals at the same frequency, but offset in phase. The cause of this subtle error is that, as a practical matter, there is a certain amount of delay through the flip-flops and feedback gate circuitry such that, under conditions of apparent phase lock, there are simultaneous "pump up" and "pump down" pulses of a width which cannot always be assumed to be infinitesimally narrow. While it might be thought that these pulses would merely cancel out, it has been found that such is not the case for critical applications because of inherent differences between the two sides ("pump up" and "pump down") of the phase detector circuitry. Usually the dominant imbalance is that the voltage midpoint between the respective active levels for the "pump up" and "pump down" pulses (logic "1" for one and logic "0" for the other) is not the same as the threshold midpoint at the error input to the amplifier component of the phase locked loop. The result is the aforementioned phase offset between the reference and the local frequency signals at apparent phase lock.
While this error is always present in the dual flip-flop phase detector type of phase locked loop, it is only when the duty cycles of the simultaneous "pump up" and "pump down" pulses become a significant portion of the total cycle time that it must be taken into account, and the critical point must be determined for each application because of such variables as the amount of phase offset which can be accommodated and the family of logic employed. The present invention serves to correct the error in all cases.